The present invention relates generally to the field of computer memory, and more particularly to requests within a memory protocol.
Modern computer memory and memory access protocols may be implemented by a wide variety of technologies at varying levels of abstraction. For example, high level protocols may control access to virtual memory. In low level protocols, various memory controllers, caches, and the like may control processors' access to physical memory.
Hardware Transactional Memory (TM) provides a memory protocol for use in environments with multiple central processing units (CPUs), wherein a group of instructions, called a transaction, operate atomically and in isolation (sometimes called “serializability”) on a data structure in memory. The transaction executes optimistically without obtaining a lock, but may need to abort and retry the transaction execution if an operation, of the executing transaction, on a memory location conflicts with another operation on the same memory location.
Generally, improvements to memory protocols for various environments, including virtual memory environments and hardware TM environments provide enhanced performance of the applicable computer system.